ASIC Digital Designer

The ASIC Digital Designer is a funded early-career position within CERN's HSE-TS-IMS Section responsible for designing, simulating and verifying the digital architecture of next-generation ASIC front-ends for radiation monitoring systems. The role involves preparing RTL designs for tapeout, supporting post-fabrication bring-up and collaborating with analogue, verification and SoC integration teams. The position is suited to candidates with studies focused on electronics and experience with HDL design and open-source ASIC EDA flows.

Monthly net stipend (5266-5793 CHF/month), 30 days paid leave plus site closure, health insurance (for self, spouse and children), CERN Pension Fund membership, family/child allowances, relocation package, on-the-job and formal training including language classes.

Applicants must be nationals of a CERN Member State or Associate Member State; have a maximum of 2 years of professional experience since graduation by the application deadline; hold a bachelor’s or master’s degree (must not hold a PhD); and must never have had a CERN fellow or graduate contract before.

Apply online via the provided SmartRecruiters application link and submit CV (English or French), copy of most relevant diploma or certificate, and any other relevant documents.